Secure and Energy-Optimized VLSI Architecture for Edge-Enabled Embedded Systems

Abstract

Embedded systems with edges are critical in the new applications in the Internet of Things (IoT), smart healthcare, industrial automation and, cyber physical infrastructures. Such systems need to be under strict energy requirements and, at the same time, be highly resistant to tampering with their firmwares, unauthorized access, and physical attacks. Nevertheless, the majority of VLSI architectures have methods to discuss energy efficiency and security as orthogonal design constraints, resulting in inefficient trade-offs and higher overheads when implemented in resource-constrained edge conditions. The current paper suggests a safe and power efficient VLSI design that is directly aimed at edge-driven embedded systems. This proposal follows the principle of unified co-design that can be utilized to integrate lightweight hardware security primitives such as a hardware root of trust, secure boot mechanism, cryptographic acceleration with multi-level energy optimization methods, such as dynamic voltage and frequency scaling (DVFS), fine-grained clock gating, and power gating. A design methodology based on register-transfer level (RTL) is used to describe the architecture and it is implemented in industry-standard synthesis tools to make it practically feasible. A detailed analysis of the proposed design with realistic edge workloads proves that the design significantly reduces the overall energy consumption and the energy per operation relative to a nominal embedded architecture with only a low overhead in the area and performance. Moreover, the internal security provisions offer a high level of protection against high firmware-based and communication threats without negating energy high efficiency. The findings validate that security and power co-optimization in architectural settings is an effective and required process of the next-generation edge computing platforms. The proposed VLSI architecture will come up with a secure, scalable, and low-energy solution to low-latency and low-power edge intelligence applications.