Energy-Efficient Edge-AI Accelerator Design Using Reconfigurable FPGA-Based VLSI Architecture

Abstract

The rising use of edge-intelligent applications, such as smart surveillance, autonomous sensing, and industrial Internet of Things (IIoT) systems, has introduced a serious demand on energy efficient hardware platforms with the ability to run AI workloads in strict power, latency, and resource constraints. The traditional CPU- and GPU-based solutions do not always suit the edge environments because they are very energy-consuming and have lower real-time performance. In order to overcome these difficulties, this paper introduces an energy-efficient Edge-AI accelerator, which relies on a reconfigurability, FPGA-centric VLSI architecture, which has been optimized towards deep neural network inference. The architecture that is proposed utilizes parallel processing element array, data reuse based on-chip memory organization as well as configurable dataflow to ensure maximum computational throughput with minimum overhead memory access. Reconfigurability is also added on the architectural level, whereby the accelerator can dynamically reconfigurate into a different neural network workload and computation needs. It is implemented on an FPGA platform using an FPGA design flow based on a hardware-oriented design process and it is tested against simulated convolutional neural network (CNN) tasks of inference. Experimental findings indicate that the proposed accelerator can be significantly better in terms of energy use and throughput than traditional embedded processing platforms, and still be able to support real-time inference. The findings affirm that reconfigurable VLSI architectures combining with the FPGA technology have a potential and scalable solution to low power Edge-AI adoption. The presented work demonstrates the usefulness of hardware-based optimization of embedded intelligence and offers a viable basis of future energy-conscious Edge-AI systems.