Reconfigurable ASIC-FPGA Hybrid Architecture for Energy-Efficient Embedded Signal Processing Applications

Abstract

A heightened requirement of energy-efficient hardware architectures has existed in the face of the growing demand of real-time embedded signal processing in areas like IoT, edge computing, and wireless communication systems. The traditional deployments using either an ASIC or an FPGA platform are inherently limited with ASICs being high-efficiency but being slow to change and FPGAs being flexible with a higher power consumption. To overcome this problem, this paper presents a reconfigurable architecture based on an ASIC-FPGA hybrid that would deliver high performance and is optimised to use low energy in embedded digital signal processing (DSP) systems. The given architecture has a fixed-function ASIC processing core and a dynamically reconfigurable FPGA fabric that allows to efficiently run core signal processing routines which include Fast Fourier Transform (FFT) and Finite Impulse Response (FIR) filtering. A conceptual mapping plan of energy-sensitive task mapping is presented to intelligently distribute the computational job loads among the ASIC and the FPGA resources with respect to the performance and power constraint. Also, the hybrid execution model is created, which facilitates runtime flexibility to enable the system to alternate between high-efficiency mode and high-flexibility mode with insignificant overhead. Through experimental assessment, it is shown that the proposed architecture has a significant potential in terms of minimising total power consumption with respect to an FPGA-only and ASIC-only implementation. The findings demonstrate that there is a quantifiable discharge of power by up to XX percent and a significant rise of energy performance in GOPS/W without compromising the low latency and high throughput. The presented results emphasise the usefulness of the hybrid concept in ensuring a reasonable trade-off between performance, flexibility, and energy efficiency, which is why it presents a promising solution to the embedded DSP systems of the next generation.