Design and Implementation of an Energy-Efficient AI Accelerator Architecture for Edge-Based Embedded VLSI Platforms
Keywords:
AI Accelerator, Edge Computing, VLSI Design, Energy Efficiency, Convolutional Neural Networks (CNN), Quantization, Low-Power Architecture, Embedded Systems, Hardware Acceleration, FPGA Implementation.Abstract
The rapid adoption of applications based on artificial intelligence (AI) is the edge has generated a high demand in energy efficient hardware with the ability to give high performance under severe power and resource requirements. The standard AI processing platforms including the processors (CPU) and graphics cards (GPU) do not usually satisfy these needs, as they are relatively energy-consuming and slow to process. The design and realisation of a VLSI AI accelerator architecture to execute edges called on embedded platforms is presented in this paper to achieve energy efficiency. The suggested system takes advantage of a quantized convolutional neural network (CNN) i.e. MobileNetV2 architecture with INT8 precision to minimise the computational complexity and the memory requirements. An optimised hardware architecture is created that includes processing units, dataflow plans and memory reuse to reduce power. The accelerator has been developed in a hardware description language, and tested on an FPGA platform. Results obtained in experiments indicate that proposed design attains high gains on energy efficiency expressed in tera-operations per second per watt (TOPS/W), but the accuracy remains competitive. The system also has low inference latency, and therefore, is appropriate in edge applications of real time. It may be compared to conventional implementations and comes out as a promising solution to next-generation embedded AI systems as proposed architecture is more power efficient and performs better than the conventional ones.
