Beyond CMOS Scaling: AI-Accelerated VLSI Design for 3D ICs, Chiplets, and Emerging Computing Paradigms

Abstract

The scaling of CMOS has stalled, the architecture of VLSI is becoming more about integration
and design automation beyond the Moore’s law. The 3D (3-dimensional) ICs, as well as
chiplet-based systems promise good performance and energy-saving capabilities, however,
there appear to be tightly coupled trade-offs between power, performance, area, thermal
behavior, and reliability that these systems complicate the standard automation of electronic
design (EDA) through its heuristic approaches. The paper provides a single-stop AI-accelerated
VLSI system methodology in post-CMOS system designing, where machine learning,
reinforcement learning, and graph-based models are applied in the process of designing
the behaviour of the system in design space exploration, physical implementation, and new
computing paradigms. The suggested model creates the flexibility to use multi-objective
optimization, physical design that is thermally and reliability conscious, and hardware-alpha
co-design, specifically designed to work with 3D IC and chiplet platforms. It goes further to
introduce emerging paradigms as in-memory and neuromorphic computing as methodology.
It is found that experimental findings are better power-thermal-performance efficiency,
decrease in design closure time, and a higher level of reliability than traditional EDA flows
proves that AI is a first-class design primitive in next-generation VLSI systems.