Learning-Guided VLSI Design Automation: AI-Driven Optimization of Power, Performance, and Area in Advanced Nodes

Abstract

Such high scaling of whichever node of semiconductor technology has greatly complicated
the process of modern VLSI design making it very difficult to balance power, performance
and area in a way that best optimizes power performance and area amidst tight design
schedules and land use by conventional rule-based electronic design automation (EDA)
workflows. Conventional heuristic based optimization models have a weakness of inability
to scale effectively, poorly exploring design space and time to converge especially at the
deep scaled technology nodes. In order to overcome these shortcomings, this paper presents
a learning framework of VLSI design automation that incorporates the machine learning
methods at both the synthesis and physical design phases to support predictive and adaptable
PPA optimization. The proposed methodology uses design data collected in effect through
intermediate EDA phases to train learning models that are capable of predicting with high
accuracy timing, power, and area measures to be utilized in directing design choices within
an iterative optimization cycle. The framework conducts a proactive process of influencing
the EDA process by integrating data-driven intelligence into an explicit design process to
achieve a better convergence and less dependency on manual tuning. When experimental
appraisals are performed on representative benchmark digital circuits executed at advanced
technologies nodes, the enhancement in power efficiency, timing closure, and the area
usage is consistently greater when compared to the conventional non-AI-driven EDA flows.
Also, the learning-guided approach has a great effect, it minimizes the amount of design
cycles necessary to reach closure, which demonstrates the benefits of the guiding design
approach in speeding up the design turnaround time. The findings confirm that learning
driven automation offers a scalable, effective, and viable learning-solution to the design
processes of the next generation VLSI design-flow addressing the advanced semiconductor
technologies.