Reinforcement Learning-Driven Design Space Exploration for Power-Performance Optimization in Advanced VLSI Architectures

Abstract

The complexity of the advanced VLSI architectures has greatly enhanced the design space exploration (DSE) methods to be efficient in exploiting the power-performance-area (PPA) trade-offs. Traditional heuristic and metaheuristic algorithms like genetic algorithms and simulated annealing tend to be limited in scaling and slow convergence in high-dimensional design spaces. In response to these issues, the paper suggests a reinforcement learning (RL)-based DSE model to multi-objective optimization in current VLSI systems. The given strategy makes DSE a sequential decision-making task, allowing an RL agent to conduct a series of tests and optimizations of architectural structures. The model is based on Deep Q-Network (DQN) and is used to learn the best design policies and interact with an evaluation environment with simulation. Reward function incorporates a combination of power, delay and area metrics to direct the agent towards a balanced optimization. Standard VLSI benchmark circuits are synthesized on a platform based on a 28 nm FPGA technology and are experimentally verified. Findings show that the given approach provides up to 28.6 and 19.3 percent power consumption and delay reduction in comparison to traditional methods, respectively, and competitive area overhead. The RL-based framework also converges quicker and has better adaptability. Such results affirm the usefulness of RL-based methods towards scalable and intelligent VLSI design automation.