Design and Optimization of Low-Power High-Performance VLSI Architectures for Next-Generation SoC Systems

Abstract

The emerging use of artificial intelligence, Internet of Things (IoT), and edge computing among other applications has exerted increased pressure on the energy efficiency of VLSI systems, whereas the increasing demand of high-performance System-on-Chip (SoC) systems has increased demands on efficient energy consumption of VLSI-based architecture. Although, with more leakage currents, technology scaling constraints and dynamic workload changes, finding an optimal tradeoff between power consumption and performance is a significant challenge. This paper gives the designing and optimization of a hybrid low-power high-performance VLSI architecture that combines adaptive power gating and dynamic voltage and frequency scaling (DVFS) approaches. The proposed design is a dynamic way of controlling the various components of power both at the static and dynamic state; idle circuit blocks are selectively disabled, and operating voltage and frequency are adjusted to the current workload situation in real-time. A 45 nm CMOS technology node is used as an implementation and evaluation tool of the architecture in a simulated environment based on Cadence. Results of simulations prove that the suggested design reduces power consumption by about 32 percent and propagation delay by 18 percent, over traditional architectures. Moreover, there is also a major decrease in the power to delay product (PDP), which implies increased energy efficiency. The suggested architecture can provide a scalable and efficient architecture to address the next-generation SoC systems with providing high computational speed and adhering to strict power constraints, which makes it applicable to the current energy-sensitive electronic uses.