Variation-Aware VLSI Design Methodology for Reliable Nanoscale CMOS Circuits

Abstract

Circuit reliability, timing performance and predictable overall design have become important issues in nanoscale CMOS technologies due to process variations that substantially impair these parameters. The traditional deterministic design methods do not sufficiently incorporate the effect of parameter variation like threshold voltage, channel length and variations in supply voltage. The VLSI design methodology, which considers variations to improve reliability with process uncertainty, is presented in this work. The method uses Monte Carlo simulation to predict statistical variations and the behavior of a circuit over a large set of operating conditions. The delay is analyzed in detail to measure mean delay, variability and distribution measures to enable accurate evaluation of timing performance. The suggested scheme uses design optimization approaches in order to reduce the variability of delays and enhance resilience. Experimental evidence shows that timing yield is much improved, and the variability of delays is much reduced, relative to traditional design techniques. The results affirm that the proposed methodology offers a simple and scalable way in designing reliable nanoscale CMOS circuits under uncertainty so it would be most appropriate in next-generation high performance and low-power VLSI systems.