Runtime Reconfigurable FPGA-Based Architecture for Adaptive Hardware Acceleration in Real-Time Systems

Abstract

FPGAs have become a potent hardware acceleration platform; more traditional, highlevel FPGA architectures are characterized by low flexibility in dealing with dynamic and heterogeneous real-time tasks. Such a drawback results in the inefficiency in the use of resources and the suboptimality of performance in adaptive computing environments. This paper proposes a runtime reconfigurable FPGA-based architecture to solve these challenges so that the real-time systems can be adaptively hardware accelerated. The given framework takes advantage of dynamic partial reconfiguration (DPR) to reconfigure hardware modules dynamically to be able to efficiently switch between tasks without stopping system operation. Moreover, an adaptable scheduling algorithm is presented to schedule tasks intelligently considering the nature of work, availability of resources and overhead of reconfiguration. The system is tested with representative workloads and proves to have improved performance greatly compared to the traditional static designs. Experimental data indicates that there is significantly a lower execution latency, improvement in throughput, and energy efficiency as resources are optimally used and idle hardware is minimized. The proposed architecture has a good balance of both performance and flexibility and can be used in next-generation real-time application like edge AI, signal processing, and embedded systems. Within the context of the above, this work provides a scalable and efficient reconfigurable computing platform that takes the state-of-the-art in adaptive FPGA-based acceleration.