S. PRAVEEN KUMAR. Algorithm–Architecture Co-Design of High-Throughput DSP Hardware Accelerators for Next-Generation Embedded Systems. Journal of Integrated VLSI and Signal Processing, [S. l.], v. 1, n. 1, p. 26–34, 2026. Disponível em: https://iaeces.com/Index/index.php/JIVSP/article/view/48. Acesso em: 1 aug. 2026.