Hardware-Efficient VLSI Design of AI-Enhanced Signal Processing Pipelines for Resource-Constrained Platforms

Abstract

Cross-sectional adaptability, accuracy, and robustness of embedded and edge computing
applications have been facilitated by the growing use of artificial intelligence (AI) in signal
processing. However, the real implementation of AI-enhanced signal processing pipes
on resource-constrained environments is still a major challenge because there are strict
constraints on power consumption, silicon area, memory bandwidth, and real-time latency.
The paper has offered a proposal of a set of hardware effective VLSI design methodology
used to design AI-enhanced signal processing pipelines specifically designed to run on low
power, resource-limited embedded systems. The suggested approach assumes an algorithm
hardware co-design architecture which narrowly wraps traditional signal preprocessing
phases with a slim AI inference device as part of a profoundly-pipelined and parallel VLSI
design. In order to realize high hardware efficiency, it uses multiple hardware considerations
such as fixed-point arithmetic, quantization-aware model design of AI models, dataflow
pipelining that is optimized, and buffering strategies that have low memory usage. The entire
architecture is derived on an FPGA platform and tested on post-implementation conditions
in order to provide realistic performance evaluation. It has been experimentally shown that
the proposed architecture provides significant gains in throughput and energy efficiency
over traditional non-optimized and non-AI baseline architectures with competitive inference
accuracy. These findings affirm the tight design of AI inference through a hardware-optimized
signal processing pipeline to highly decrease the latency and resource overhead. All in all, the
suggested VLSI architecture offers a relevant scalable solution to making real-time AI-assisted
signal processing possible in resource-constrained embedded and edge systems.