Algorithm–Architecture Co-Design of High-Throughput DSP Hardware Accelerators for Next-Generation Embedded Systems

Abstract

The next-generation embedded systems are becoming more called upon to accommodate
real time and high throughput digital signal processing (DSP) applications to be executed
with exceedingly tight limitations on power consumption, latency and silicon area. DSP
implementations realized in conventional software running on general-purpose processors
and embedded CPUs can generally not meet these very high performance requirements.
Hardware accelerators are potentially a solution however, it is of critical importance that
the alignment between the algorithmic features and the architecture design decisions is in
place. Here, algorithm-architecture co-design has become an important paradigm towards
realization of optimized application-specific DSP hardware. The paper will provide a co-design
hardware accelerator algorithm architecture approach to the design of high-throughput DSP
hardware accelerators optimized in the future generation embedded systems. This design
is a joint optimization of signal processing algorithms and hardware design which combines
the algorithm-level transformations, parallelism exploitation, pipelined data-path design,
and architecture-sensitive memory optimizations into a single design flow. An accelerator
architecture based on the scalable and modular design of DSPs is created, which allows
the flexible parallelism and data reuse. The proposed architecture is validated by mapping
representative DSP Kernels such as finite impulse response (FIR) filtering and fast fourier
transform (FFT) on the proposed architecture. The accelerator is designed on an FPGA
platform, and experimental assessment is done to appreciate throughput, latency and
energy efficiency. The performance and energy efficiency results are shown to be immense
in comparison with traditional baseline architectures that are not optimized by co-design.
These results affirm that an algorithm-architecture co-design is a successful approach to
the implementation of a high-performance and energy-efficient DSP accelerator in next
generation embedded system.