Low-Power Embedded VLSI Architectures for AI-Driven Signal and Image Processing Systems

Abstract

The heavy increase in artificial intelligence (AI)-driven signal and image processing on
embedded systems and edge-based systems has further increased the urge to utilise
energy-efficient very-large-scale integration (VLSI) architecture. Traditional processor based
solutions are too slow in moving data and energy proportional which corresponds to an
inappropriate solution in power-constrained systems. The present paper discusses a low
power embedded VLSI architecture that is optimised to be used in AI-based signal and image
processing applications with a focus on architecture-algorithm co-design and energy-efficient
optimization. A common system model is established to account dynamic and leakage power
terms and to measure energy efficiency in regards to energy / inference. The presented
architecture is a combination of specialised AI acceleration and programmable signal
processing data streams, with localised hierarchy of shared memory to minimise the overhead
of data transfer. Some energy-efficient methods, such as adaptive dataflow management,
clock and power gating, dynamic voltage and frequency scaling, and workload-aware
precision adaptation are added. Compared to the conventional architecture, experimental
analysis of the proposed architecture is able to establish similar power consumption and
energy per operation, and simultaneous competitive throughput, which confirms the use of
the proposed architecture in low-power embedded AI systems.