AI-Assisted VLSI Architectures for Real-Time Signal Processing: Algorithm–Hardware Co-Design and Optimization

Abstract

Strict hardware, wire and energy performance and latency requirements in developing
applications like edge intelligence and cyber-physical systems are hard. In many traditional
VLSI design methods, there are no connexions between the design of algorithms and the
implementation of hardware resulting in an inefficient design in real-time operating licences.
This paper suggests the use of AI-enabled algorithm-hardware co-design as an optimization
of VLSI architectures on the basis of real-time signal processing. The framework characterizes
the signal workloads, hardware resource constraints and performance objectives in a common
optimization problem specifying the energy-latency-accuracy tradeoffs. The optimization
engine is an AI that is used to search through the design space and find the best fits of
algorithmic parameters and hardware configurations. In this approach, a reconfigurable
VLSI architecture equipped with AI-controlled parameter adjustment is established to meet
real-time requirement when using parameter to different signal conditions. Experimental
findings of a representative signal processing kernels show that the energy consumption
and the latency are significantly reduced with respect to their conventional baseline design
counterparts, with no compromise on the computational accuracy. The obtained results
confirm the usefulness of AI-based co-design in the next-generation real-time VLSI signal
processing systems.