Low-Latency DSP Hardware Architecture for Real-Time Video Processing in Embedded Platforms

Abstract

Processing of real time video in embedded systems requires a substantial computation power and at the same time, a high level of latency and power constraints. The conventional digital signal processor (DSP) architectures do not tend to satisfy them because of the lack of parallelism and ineffective memory access patterns. The present paper describes a low-latency DSP hardware architecture, which is specifically created to be used in real-time video processing in embedded systems. The architecture suggested incorporates a pipelined and parallel processing architecture as well as an optimal memory hierarchy to optimise throughput and minimise processing delay. A specific multiply-accumulate (MAC) unit is implemented at the register-transfer (RTL) level to ensure that core DSP operations are executed faster and a few circuit-level optimizations are selectively used to make switching faster and decreasing the critical path. FPGA-based design tools are used to implement and test the system with some of the key performance metrics being the latency, power consumption, and throughput. The experimental outcomes indicate that the suggested architecture can realise high processing speed and energy efficiency that are much higher than what conventional DSP implementations exhibit. The proposed architecture offers a customizable and efficient architecture to real-time, multimedia processing, such as video analytics, surveillance, and embedded vision systems.