Thermal-Aware and Reliability-Driven Floorplanning Techniques for Nanoscale VLSI Circuits

Abstract

The ever-growing nanoscale VLSI circuits have increased power density dramatically, posing intense thermal challenges like local hotspots and non-uniform heat distribution. These thermal problems have negative impacts on the performance, reliability and the lifetime of circuits. In this paper, a new thermal-conscious and reliability-oriented floorplanning method to reduce degradation caused by temperature to nanoscale integrated circuits is introduced. The suggested solution incorporates thermal modeling into the floorplanning procedure by applying a multi-objective optimization model, which takes into account physical design requirements and thermal characteristics. Important thermal parameters such as peak temperature (Tmax), average temperature (Tavg), and thermal gradient (ΔT) are included in the cost function to inform the location of modules. The process is a successful complement in redistributing high-power components to minimize the formation of hotspots, as well as enhance thermal uniformity. Also, stability is improved by correlating temperature profiles with failure models which allow superior mean time to failure (MTTF). Experimental data on standard benchmark circuits show that the given technique can reduce peak temperature by as much as 18% and thermal gradients by a wide margin over the conventional floorplanning information, without incurring significant area and wirelength overheads. In general, the proposed framework offers an effective approach to thermally optimized and reliability-conscious VLSI design, which is very applicable to the next-generation nanoscale technologies.