Sub-Threshold CMOS VLSI Architecture for Ultra-Low-Energy Embedded Processing in Sustainable Electronic Systems
Keywords:
Sub-Threshold CMOS , Ultra-Low-Power VLSI , Energy-Efficient Embedded Systems , VLSI Architecture Optimization , Genetic Algorithm (GA) , Particle Swarm Optimization (PSO) , Simulated Annealing (SA) , Power Delay Product (PDP)Abstract
The growing popularity of embedded systems that require a low power consumption in systems like Internet of Things (IoT), wearable electronics, and green computing further complicated the necessity in ultra-low-power VLSI design systems. Nonetheless, traditional CMOS architectures when working in the super-threshold region, have been characterised by high power consumption and leakage problem therefore limiting their applicability in energy-constrained applications. In order to overcome this issue, the sub-threshold CMOS VLSI architecture proposed in this paper aims to support ultra-low-energy embedded computing, with the supply voltage reduced relative to the thermal noise, and hence the power dissipation as a result decreased significantly. To additionally improve the design efficiency, optimization based strategy is also integrated employing heuristic algorithms, that is, Genetic Algorithm (GA), Particle Swarm Optimization (PSO), or Simulated Annealing (SA) to perform optimal optimization of basic design parameters, including transistor sizing, supply voltage, and threshold voltage. This optimization scheme allows a good search over the design space to obtain a good trade-off among power consumption, delay and energy efficiency. The suggested architecture shows high enhancements in the performance metrics where it showed considerable decrease on total power consumption relative to the conventional baseline design besides an increase in the energy efficiency in the form of energy per operation. Besides, the Power Delay Product (PDP) and Energy Delay Product (EDP) are also seen to have significant improvements that suggest a more efficient power-performance trade-off. The obtained findings demonstrate the usefulness of sub-threshold CMOS design combined with optimization algorithms, and thus the proposed method is very appropriate to support the next-generation sustainable electronic systems as well as the ultra-low-power embedded systems.
