Thermal-Aware and Power-Optimized VLSI Architecture for Green and Energy-Efficient System-on-Chip Applications

Abstract

The fast development of System-on-Chip (SoC) devices in applications of edge computing, Internet of Things (IoT) and artificial intelligence has exacerbated issues of power consumption and heating in latest VLSI designs. High power density results in excessive production of heat which then negatively impacts the system performance, reliability and life-span. In this paper I suggest a thermal-sensitive and power-efficient VLSI architecture incorporating dynamic voltage and frequency scaling (DVFS), power gating and real-time thermal monitoring in a unified adaptive control scheme. The proposed system is based on the feedback-driven dynamic mechanism that can adapt the operating voltage, frequency, and modules activity in accordance with the workload conditions and changes in temperature inside the on-chip. Thermal sensitive control approach is employed to prevent the development of hotspots and control the leakage power that rises exponentially with temperature. The architecture is tested using simulation with different workload and analysed against the traditional non adaptive designs. Experiments show that the total power consumption is greatly reduced, thermal stability is improved as well as the energy efficiency is increased without disturbing the performance. The suggested design is scalable to and can be used in green computing applications, especially energy-constrained SoC environments like IoT and edge devices. This paper is a step towards creation of sustainable and thermally reliable next-generation VLSI systems.