Near-Threshold Voltage Based VLSI Design for Ultra-Low-Power and Sustainable Integrated Circuits

Abstract

The interstellar growth over the last few years in terms of Internet of Things (IoT), wearables, and edge computing systems has created a tremendous need to design ultra-low-power integrated circuits. A new technique that has been developed is near-threshold voltage (NTV) operation as it consumes less power because it increases quadratically with supply voltage. But the NTV operation brings challenges like propagation delay is doubled, sensitivity towards variation in processes is higher, and reliability is also low in low-voltage. This paper introduces a variability conscious near-threshold VLSI design strategy, which incorporates adaptive voltage scaling into strategy, in combination with the hybrid power management strategy, to achieve optimal energy efficiency and performance. The suggested strategy uses dynamic voltage setting that depends on the state of the workloads together with the statistical timing analysis that can alleviate failures caused by variability. The simulation is carried out in 45 nm CMOS technology and the voltage magnitude of 0.3 V to 1.0 V with some important indicators, including energy consumption, delay, and the energy-delay product (EDP). It has been successfully demonstrated that the suggested design is capable of reaching up to 65 percent of the total energy consumption and the results in an improved EDP of roughly 40 percent as opposed to conventional super-threshold designs with little effect on reliability. These results show that near threshold voltage-based design offers a viable and scalable development of efficient and sustainable VLSI systems in low-power next generation.