Thermal-Reliable VLSI Architectures for Power-Constrained Applications

Abstract

Through scaling of CMOS technologies and the accelerating growth of power constrained
applications like Internet-of-Things (IoT) devices, wearable healthcare systems, edge artificial
intelligence accelerators, and autonomous embedded systems thermal reliability has become
a preeminent challenge in the current design of Very-Large-Scale Integration (VLSI). Despite
the low-power operating conditions, the growing power density and non-uniform workload
activity result in localised hotspots and extreme thermal gradients, completely undermining
the level of performance and contributing to the leakage power problem and other hot power
related ageing effects such as Negative Bias Temperature Instability, Hot Carrier Injection, and
Electromigration. Such effects are critical debilitators of system life and reliability, especially
with surface scaled nanometer technologies with lower thermal margins. In this paper, a
detailed exploration of thermal robust VLSI architectures adapted to power-constrained systems
particularly are detailed. Thirdly, significant thermal failure modes and their consequences on
long-term reliability are examined, then architectural, circuit, and physical-design cleaning
up solutions are examined. Based on this discussion, a cross-layer thermal-aware design
framework is indicated including the adaptive voltage and frequency scaling, fine-grained
power gating, thermal-aware floorplanning, and the smart runtime management that is
stipulated by on-chip thermal sensing and predictive control. The architectural suggestion
is proactive in controlling temperature and considering energy efficiency, performance, and
reliability issues. A large scale of simulations using a 28-nm CMOS technology node and
representative workloads with low power usage indicate that the proposed framework can
contain hotspots, which can significantly reduce peak temperatures by up to 25% and mean
time to failure by 2030 positions by almost 7% overhead and insignificant performance loss.
The findings confirm the appropriateness of the proposed thermal-reliable VLSI architecture to
the next generation energy-constrained systems that would be highly reliable and have long
operational life.