PPA-Optimized VLSI Architecture for Energy-Efficient Digital Systems

Abstract

The growing need in small and high-density electronic devices has increased the significance
of the design of power-constrained and performance-efficient Very Large Scale Integration
(VLSI) architectures. The conventional methodologies used in the design of VLSI typically
focus on performance improvement, which further induces power consumption and
thermal reliability degradation thus negatively affecting the scaling of the current energy
starved systems. This study introduces a new VLSI Power-Performance-Area (PPA) optimised
architecture which strategically combines multi-level power saving methods and adaptive
performance scaling and area-aware design with regard to these issues. The suggested
architecture integrates volatile voltage and frequency adjustment (DVFS), micro-gated
power gating, and near-threshold functioning so as to allow smart power management of
a wide range of workloads. A common design architecture is used, in which power and
performance trade-offs are dynamically tuned with the balance at the hardware level and
area efficiency optimized with the help of logic sharing and small memory designs. Industry
standard simulation and synthesis of the architecture is carried out on a 45nm CMOS process,
and shows significant improvements in the energy efficiency and PPA measurements. The
proposed structure can reduce total power by up to 38 watts, performanceperwatts by 42
percent, and retain area overhead, as a result of architectural reuse, within 5 per cent of a
traditional baseline architecture. Besides, the architecture will be operationally integrity in the
near threshold voltages, therefore the architecture will run low on energy without any critical
level performance loss. The PPA-optimised-based approach in this work is scalable and is
applicable to a large variety of embedded and edge computers whose energy sustainability,
small silicon protocols, and reliable performance is paramount. The research paper is a
holistic approach and previously tested findings that present a viable solution to existing VLSI
design bottlenecks as part of the trend towards green and sustainable computing. The results
provide a good basis upon which new studies in AI-based dynamic power management and
cross-layer optimization of energy-conscious VLSI systems can be conducted.