Reliability-Constrained Low-Power VLSI Design Using Adaptive Body Biasing

Abstract

As technology scales to deep-submicron regimes with aggressive technology, VLSI circuits present urgent issues of increasing leakage power, variability in their processes and degradation of long-term reliability. Adaptive Body Biasing (ABB) has proved to be a valuable method of dynamically adjusting the threshold voltage in order to make power-performance trade-offs. Nevertheless, ABB traditional methods pay little attention to reliability constraints, including Bias Temperature Instability (BTI) and threshold voltage changes caused by aging, which restricts their use in the long term. In this paper, the reliability-constrained low-power VLSI design framework is introduced, which is founded on adaptive body biasing to trade-off leakage power, propagation delay, and device lifetime. An analytical model that unites body-bias-dependent change in threshold voltage, subthreshold leakage properties, and time-dependent aging effects is created. The suggested solution uses dynamic bias change due to workload parameters and predicted aging degradation to assure the best performance under reliability limitations. Simulation outcomes of a 14 nm CMOS technology show that the intended method yields up to 45 percent of leakage energy reductions and delay overhead at the expense of 7 percent, as well as increased lifetime of the devices by about 25 percent relative to traditional method of bypassing the fixed-bias approach. These findings focus on the usefulness of the reliability-conscious ABB as a scaling solution to next-generation energy efficient VLSI systems.