Energy-Efficient Multi-Core VLSI Architecture for High-Performance Embedded Applications

Abstract

Embedded systems and high-performance applications causing growing computational requirements have greatly increased power consumption in multicore VLSI architectures, posing serious problems in energy efficiency and thermal management. In this paper, the authors describe an energy-efficient multi-core VLSIarchitecture that is optimized to support high-performance embedded systems. To
define dynamic power consumption in many processing cores, a mathematical model of power is created that describes power consumption dynamically and an advanced workload-sensitive control policy is introduced that can use dynamic percore voltage and frequency adjustments. The suggested architecture incorporates dynamic allocation of tasks, per-core Dynamic Voltage and Frequency Scaling (DVFS), and feedback-controlled performance feedback to attain optimal use of energy in different workload situations. This framework is tested on a hybrid simulation and FPGA-based validation environment with compute-intensive, memory-intensive and a mixed workload. Experimental measurements show that up to 38 percent of power savings and 35 percent of overall energy efficiency improvement over conventional static and global DVFS-based multi-core systems is achieved with a 68 to 8 percent degradation in performance. The findings validate the claim that coordinated scheduling of tasks and per-core DVFS play an important role in improving the energy performance trade-off. The given architecture offers a scaleable and viable design solution to next generation energy-constrained embedded VLSI systems.