Dynamic Voltage and Frequency Scaling-Based Energy Optimization in Modern VLSI Architectures

Abstract

Increasing complexity and power density of contemporary VLSI architectures has aggravated the necessity of effective energy management approaches. Dynamic Voltage and Frequency Scaling (DVFS) has turned out to be one of the best methods of minimizing dynamic power consumption without compromising on system performance. This paper suggests a workload-conscious DVFS-based energy optimization model of current VLSI systems. A mathematical power model is created to describe the response between voltage, frequency, and dynamic power consumption, and an adaptive control policy is created, which dynamically chooses optimum operating states, depending on instantaneous workload conditions. The suggested framework is tested with the help of simulation-based testing in the conditions of compute intensive, memory-intensive, and mixed workloads. The experimental findings suggest that the suggested DVFS algorithm can reach the power consumption reduction of up to 35-40 percent and energy efficiency increase of up to 30-38 percent over the traditional static and non-adaptive DVFS algorithms, and performance loss can be controlled to 5-7 percent. The findings indicate the efficiency of workload-sensitive scaling in generating energy efficiency and computation speed. The suggested framework can be scaled and incorporated into future energy-limited VLSI platforms, such as embedded processors and IoT devices.