Leakage Power Reduction Using Adaptive Power Gating Techniques in Green VLSI Systems

Abstract

Leakage power has become a vital problem in deep submicron VLSI systems with the aggressive technology scaling, and it is now an important factor affecting overall energy efficiency and thermal reliability. The more traditional methods of power gating though useful to a certain degree are usually constrained by the issue of the lack of a static control as well as undesirable tradeoffs between performance and power savings. In this paper, I would suggest an energy-efficient solution that depends on Multi-Threshold CMOS (MTCMOS) with an adaptive power gating mechanism, the use of dynamic sleep control to reduce the leakage power without compromising system performance. The suggested approach applies workloadaware sleep transistor switching, which is based on the principle of constant monitoring of the activity of some circuit to switch between the active state and the sleep state, preventing the unnecessary use of power during idle states. The simulation results show that leakage power is reduced significantly (by up to about 40- 60 %) and Power-Delay Product (PDP) achieves impressive improvements over traditional methods. Improved latency of wake-ups and better operational stability is also guaranteed by the adaptive framework. In sum, this solution offers a practical trade-off between power performance and efficiency enabling it to be extensively used in green, energy-efficient VLSI systems in the next-generation embedded systems and IoT applications.