Thermal-Resilient and Energy-Aware VLSI Design Framework for Sustainable Embedded Intelligence

Abstract

The current high rate of embedded intelligence development in edge computing, IoT (Internet of things) and autonomous systems, and smart healthcare systems has added significantly to the computational complexity and power density of contemporary Very Large Scale Integration (VLSI) systems. Nevertheless, high power leakage, hotspots, and leakage current are still vital issues that restrict the reliability, long life, and performance of embedded computing systems. Traditional lowpower VLSI designs typically concern one of the two, energy optimization or thermal management, leading to diminished reliability and poor use of resources. The article offers a thermal resilient and energy conscious VLSI architecture of a sustainable embedded intelligence system that co-optimizes power efficiency, thermal stability and computational performance. The framework suggested merges the adaptive dynamic voltage and frequency scaling (DVFS), thermal-conscious task scheduling, multi-threshold CMOS (MTCMOS)-based leakage optimisation, and smart workload migration into a single architecture. A hierarchical thermal-monitoring system measures on-chip temperature distributions continuously and dynamically enables mitigation measures to inhibit the formation of hotspots. A 45 nm CMOS technology model is used with embedded artificial intelligence workloads to evaluate the framework. Expertise of the experiments show that the dynamic power consumption and leakage power consumption are substantially reduced and system reliability and energy-delay product is enhanced. The comparison and analysis prove the suggestions presented in the paper to be an effective and sustainable solution to the next-generation intelligent embedded VLSI systems.