Sub-Threshold CMOS VLSI Design for Sustainable and Energy-Efficient IoT Devices

Abstract

The fast growth of Internet of Things (IoT) devices has focused pressure on most of the low-power VLSI systems designed to be operated with stringent energy limits. The traditional CMOS design, however, has a major power consumption problem, making it unsuitable in battery-powered and energy-harvesting applications. This paper suggests a sub-threshold CMOS VLSI design framework coupled with multi-objective optimization methodology to realize increased energy efficiency. The proposed method uses sophisticated optimization methods like Non-Dominated Sorting Genetic Algorithm II (NSGA-II) and Multi-Objective Particle Swarm Optimization (MOPSO) to strike a good balance between the power consumption and the propagation delay. Also, low-power design techniques such as Dynamic Voltage and Frequency Scaling (DVFS), Multi-Threshold CMOS (MTCMOS), power gating are also adopted to reduce leakage and dynamic power dissipation even more. Key metrics are used to measure the performance of the proposed architecture and they include power consumption, delay, Power-Delay Product (PDP) and Energy-Delay Product (EDP). The results of simulation show that there is a significant decrease in the total power consumption and significant increases in energy efficiency in comparison with traditional designs. The designed optimization is a balanced trade-off on the performance and power, which ensures that it is very applicable in the next-generation ultra-low-power Internet of Things.