Energy-Aware Power, Performance, and Area Optimization in Nanoscale VLSI Circuits Using Multi-Objective Optimization Techniques

Abstract

The quick up-scaling of nanoscale VLSI technologies has contributed to a high power density and provided a very crucial challenge in obtaining an energy saving and high performance circuit design. The paper describes an energy-conscious optimization model to optimize the power, performance, and area (PPA) of nanoscale VLSI circuits. To search the design space and find the optimal tradeoffs between conflicting objectives, a multi-objective optimization algorithm, which is founded on evolutionary algorithms like NSGA-II and Particle Swarm Optimization (PSO), is used. The suggested methodology will combine the sophisticated circuit-level methods, such as Dynamic Voltage and Frequency Scaling (DVFS), power gating, and Multi-Threshold CMOS (MTCMOS), to successfully decrease the dynamic and leakage parts of power. Extensive simulations show that the overall power consumption is considerably reduced as well as the essential energy efficiency indicators like Power-Delay Product (PDP) and Energy-Delay Product (EDP) are increased, without sacrificing acceptable performance or area overhead. These findings confirm the usefulness of the suggested multi-objective framework to produce well-balanced and scalable energy-efficient VLSI models to be highly applicable in next-generation low-power embedded and edge computing tasks.