Ultra-Low-Power Near-Threshold VLSI Architecture for Energy-Constrained Embedded Systems

Abstract

The demand on ultra-low-power VLSI architectures has increased due to the fast growth of energy-constrained embedded systems such as IoT nodes, wearable computing devices, and edge computers. Traditional CMOS architectures have high amounts of dynamic and leakage power dissipation, which restricts their use in battery powered devices. The present paper presents a low-cost near-threshold VLSI System-on-a-chip design, which combines several different methods of power optimization to obtain significant energy savings. The proposed design works within near-threshold voltage range and uses dynamic voltage and frequency scaling (DVFS), power gating, multi-threshold CMOS (MTCMOS), and clock gating to reduce the dynamic as well as the static power consumption. The control operation adapts operating conditions dynamically to changes in workload, allowing adaptive power-performance trade-offs. The results of simulations have shown that the total power consumption is reduced greatly, and the energy efficiency measures like Power-Delay Product (PDP), and Energy-Delay Product (EDP) are improved significantly over conventional designs. Though the near-threshold operation also brings about a bit of overhead in the delay, the given architecture provides the best solution to balance between power savings and performance. The findings prove that the given strategy is quite appropriate to next-generation embedded systems with ultra-low power consumption, long, energy-conscious calculation, and long operational life.